ICC scenario

set_scenario_options:    

 -cts_corner min | max | min_max | none
              When set to min (max), the min (max) corner of the scenario will
              be considered by the optimize_clock_tree command.  When  set  to
              min_max, both of the min and max corners of the scenario will be
              considered by the optimize_clock_tree command. Default value  of
              this option is none.

40nm spacing rules ..........

The reason I found the following problem is that I have metal1 gap between standard cell row and the dro cell which is not really a macro, which is built from standard cell.
________________________________________________


Filler insertion. the 40nm minimum spacing  rule is  2 placement grid. which is 0.28.

The problem is when the space is say, 4 x 0.14, you have 3x filler cell in your list, 3x is chosen first, then only 1x space is left. You have a gap left.  This part is relative easy to resolve by controlling the size of standard rows, make the size always even number of 0.14. But it will become impossible after you place the standard cell, you can't control the gap between standard cells, it could be 2,3,4,5,6.

Because of the above reason, Synopsys creates this option -no_x1, which is to resolve the issue I mentioned above. It could resolve like 4x gap, it will try 3x filler, then use two 2x filler to fill the gap.

ESD and DRO cells

These two cells are user friendly cells, they don't use metal4. They follow standard cell rails.

DRO used up to metal3, composed by standard cell. So I will treat it as standard cell, I won't add any blockage,  any route_guide to it, I will let ICC to take care of everything. The only thing I need to take care is to make sure the cell is on the right row and make sure the hookup won't be messed up.

    metal1 is run all the way across the block, so no need to take care the

    To play safe which is not super necessary. create_preroute_via   from metal6 to metal3

ESD used up to metal2. Two set of pins, VDD/VSS and VDD_ESD/VSS_ESD, since there is only one set of VDD/VSS here, so the connect is simple. Here is the deal, pease ESD as standard cell, make sure it is on the right row. After all the conn

    metal1 rail is only on the boundary, so some trouble over there.

     create_preroute_via  from metal6 to metal2 for VDD_ESD and VSS_ESD

Found out no need to take care the connection from upper metal to lower metal, the tool is smart enough to take care of it by itself. Walla, ICC.

I still want to take care WPE for around these blocks.

Small problem, there is no odd width filler cell in daxing's script, this may create gap for power rail. The problem is not that small, need to tell him to fix it.

spacing rule and wpe

Macro/memory:

    Side is easy,  keep 0.28, use spacing rule to make sure this, then 2.1 wpe blockage. ( No, I will not use spacing rule, I will use blockage to make sure that )

    Top and bottom, basically, need 1.5 rows to 2 rows to make sure M1 rails are there for the one row for add filler cells.

   Then there will be no spacing rule to SNPS.

Boundary boundary to meet the wpe rule:

    Top/Bottom: one row will be blocked for placement, these will be wpe blockage, remove and put back.

    Left/Right: 2.1um wide straps placement blockages will be added.

The blockages generated from addM5_xxx:

    Will be removed permeability.

My blockage:

    1. regular placement blockage:  snap to standard cell placement grid and wpe blockage will generated around it.

    2. core-area blockage: will be generate from my placement blockage gen script.

Tap cell:

     Same as before to play around the blockage, reversed blockage to place the tape cell, But I will improve the generating of the blockage to be snapped to 0.14 placement grid.

    I could have another way to place the tap cell without using blockage, I could use step to place the tap cell in the right place. And I could use spacing rule to push out other function cells next to tapecell.



  
  

09_27_2010 notes

w/spacing rules:

   gater_en   -180ps
   CoreClk  -156ps
   macro_out   -122ps

  TNS  -169ns

   skew  214ps


w/o spacing rules


    gater_en -153ps
    CoreClk  -123ps
    macro_out   -90ps
    TNS    -131ns

    Skew: 186ps


Plan and misc:

    svn, grep
    Anyway, the golden goal is to refer to that fp easily.

    netlist/sdc:  relative static

    xgdai way:   write out a floorplan and read back the floorplan.

    netlist: better attach a date with it.

     Build a touch README file, so that I could do a quick visual check.

09_21_2010 Mis

create scenario ......

09_24_2010

Mis:

What is your best features ?

Passionate, energetic and a great leader - the French don't do humble.