07_29_2010 Router options

 set_route_flip_chip_options

 set_route_mode_options

            zroute true or false.

 set_route_opt_strategy

 set_route_options  

 set_route_type      

           signal, clock or pg.

 set_route_zrt_common_options

 set_route_zrt_detail_options

 set_route_zrt_global_options

 set_route_zrt_track_options

07_28_2010 Expected Delivery from FE

1. netlist 
2. sdc file
3. scandef
4. clock exception list

Option

1. upf file
2. floorplan suggestion

07_28_2010 Bi-Weekly CAD meeting

The topic today is about the analog IP hookup

Concerns I collected from the meeting:

PLL

• It still could be rotated for now, it can't be rotated for 28nm
• All the analog signals are on the right, the digital signals are on the left.
• There is no build-in AVDD, AVSS pad, there are multiple avdd/avss ports/pins. It is up the PnR engineer to hook the ports to the PAD. Goal: resistance, IR drop.
• Three critical signals: REFCLKIn, CLKOUT_ANA, TP ( test point ). You can't have floating TP.
• PLL could be placed in the middle for flip-chip.
• The driving strength for the DCLK is x12, but there is no liberty file for PLL since there is no timing information for PLL and we don't need timing information for PLL. 

Serdes PHY routing channel

• Critical signals: clk and the current sources
• Routing channel cells are created to standardize the routing. To guarantee the quality. 
• 1um, 2um, 10um width routing cells, and the turning up/down routing cells.
• 1um, 2um cells don't have base layer, so they could be overlapped. 
• Different kinds of routing channel and buffer cells.
• You need a clock buffer every 500um, but you need place the 1st buffer 250um away since there are around 250um routing inside PHY.

COMPHY

• The power PADs are built-in, so no need to worry about AVDD/AVSS hookup.
• One guy complained about the misaligned pad or something, another person suggested it is because of the multiple pieces of metal for the PAD
• Chengpei complained we don't see the power mesh in the digital portion of the PHY, so this makes our IR analysis very difficult to give us last minute surprise. 

07_28_2010 ICC

07_22_2010 IR drop / power structure study

Both GC and ISP have M7 on top, but you can't expect this all the time, it is a bonus and keep changing. M7 is just for vcc_block.

Both GC and ISP are in the switching power domain, this means they have always on and switching power. vcc_m1 ( always on ) and vcc_block.  The role of vcc_m1 is to supply the power to the always on power part and the power switch cell. vcc_m1 is relative straight forward. vcc_block is tricky.

GC, power distribution structure:

           M6, M4 vertical straps.  M6 strap width is 5um, M4 strap width is 0.4um.

           There are twice M4 straps than M6 straps. half of the M4 straps are in between M6 vcc_gc and vss straps. The structure is solid. M4 straps are connected to M1, M6 is connected to M4. For the in between M6 strap M4s, the power is solid. For the "floating" M4s, they connected to the power network through M1 ( what a shame ).

           For the macro region, M5 horizontal straps are added. Macro picked up the power through M4 pins, then M5 horizontal straps, then M6 the main power straps. The power is ok or solid for macro.

  note for GC: there is a weak spot for a small area between marcos. IR drop is big, reason, there are M4 straps but it is not connected to M6 directly, the connection is like this:  M4 picked up the power from M1 and distributed to other M1 ( stdcell ),  I guess Da Xia made some last minute fix, he extended M5 straps of Macro to connect these M4s.

ISP power structure:

          Three layer power network. M6 and M2 are vertical ones. M5 is the horizontal. It is a three layer power mesh. M2 is not needed to align with M6. It is a very solid three layer power network. No special treatment is needed for macros.

    note for ISP: need to make sure there are Power Switch cell in between macros ( both horizontally and vertically , Ki-Tae only guaranteed horizontal switch cells, I think the IR will be better with switch cells vertically in between macros ). need to make sure at least a pair of M2 straps in between macros.

So Jeffrey's power mesh

1. Three layers M2, M5, M6 
2. I will use less dense M6 then ISP to give back M6 routing resource.
3. Make sure the gap between macros is wide enough for one row of switch cell
4. Make sure the gap between macros is wide enough for one column of switch cell
5. Make sure the gap between macros is wide enough for one pair of M2 straps
6. Make sure the gap between cell and boundary is wide enough for power switch cell
7. Add vcc_block, vss ring around the block.

07_20_2010 Macro hier count

1 b2d/fe

2. b2d/hi

16. b2d/mc

29. b2d/pe

2. b3d/pa

14. b3d/ra

10. b3d/se

41. b3d/sh

9. b3d/tx

07_20_2010 Power connection

stdcell: VDD/VSS ( vcc_gc/vss )

power switch cell: VDD/TVDD/VSS ( vcc_gc, vcc_m1, vss ) NSLEEPIN NSLEEPOUT

ESD: VDDON/VSS ( vcc_m1, vss )

DRO: vcc_m1/vss ( vcc_gc, vss )