TIMING RESULT

Top path: 627 Mhz, assume target is 650 Mhz, we will have violation with ~50  paths.  Top path is -119ps.

The above is for placement database.


TODO:

Check CTS TIMING RESULTS AND KICK OFF ROUTE ........

08_23_2010 Thoughts

How much planning is enough planning ? Enough to push it out of your mind.

Report your progess

Communicate with your coworkers .........

Basically, keep every body informed.

CTS

  gfx3D_gc_pm_0 pm ( .resetRaw_(resetRaw_), .clk_fe(clk_fe), .clk_sh(clk_sh),
        .clk_pa(clk_pa), .clk_se(clk_se), .clk_ra(clk_ra), .clk_tx(clk_tx),
        .clk_pe_3d(clk_pe_3d), .clk_pe_2d(clk_pe_2d), .clk_pe_2x_2d(
        clk_pe_2x_2d), .clk_mc(clk_mc), .clk_de(clk_de), .clk_hi(clk_hi),

looks like pretty much all the clocks are generated from the pm module.

Runtime for CTS: 

                    Information: T4    CPU:  19903 s ( 5.53 hr) ELAPSE:  20770 s ( 5.77 hr) MEM-PEAK:  9750 Mb   Wed Aug 18 17:49:04 2010  (PSYN-508)

08_16_2010

GC1000 hierarchy

  b3d

  b2d

08_12_2010 PDS

symbol libraries:


/proj/pnreda/SYNOPSYS/ICC/2010.03-SP2-1/libraries/syn/gtech.db
/proj/pnreda/SYNOPSYS/ICC/2010.03-SP2-1/libraries/syn/standard.sldb

08_12_2010

  $MKY(floorplan_file) == /proj/bg2z0scl/wa/jeffrey/design/gfx3D.current/mky/datain/brf_dsp_icc.fp
  $MKY(strmoutmap) == /proj/bg2z0scl/tech/Z0/mky_m9.strmoutmap
  $MKY(preroute_file) == /proj/bg2z0scl/wa/jeffrey/design/gfx3D.current/mky/datain/brf_dsp_icc.pr

command: id


uid=6638(jeffrey) gid=11390(bg2z0scl) groups=10(staff),150(gcad),1807(vsyslib0),11178(bg2z0),11390(bg2z0scl)

08_09_2010 New project

Devang is quick.

I need to change my mindset, from perfect to "good enough". You don't need to get something to be perfect. First, there is no such thing called perfect. You need to get it DONE quickly and then move on. Quite a few new interesting things to learn. GO FOR IT, JEFFREY.

08_05_2010 ICC Power thing

After so many days, and after so many trials. I think I am pretty comfortable for ICC.

ICC is a complicated, but very very powerful tool if you know how to manage and use it.

Here are some notes for my recent power trial for GC:

•  GC has two group of IOs, each group needs ISO cells. 
•  ISO cells will lie in the space of always-on, so we have the problem disjointed voltage area.
•  ICC supports disjointed place_bounds, so Da ignored the voltage area and used placed_bounds to put the ISO cells in the place_bounds. Then he build the buffer tree for the iso ctrl, then he updated the place bound to include the buffers. After everything is done, he manually hooked up the power for these two disjointed area.
• Note: place bound only takes leaf cells, voltage_area, power_domain only take hierarchical cells.  
• GC rtl hier is bad, but it is managable.

________________________________________________________________________

From the above notes, I did the following way. I used the UPF mode for ICC:

     Step 1:  build the correct buffer tree for ISO network:

• no power domain, no voltage area, everything is default. There is no difference between ISO cell and other regular standard cells.
• Create the place_bounds which is exactly same as the future voltage area. 
• The place_bounds is for the ISO cells.
• create_fp_placement to have all the ISO cells inside the place_bounds.
• To have prefix the newly created cell   set compile_instance_name_prefix i_iso_buffer_  
• create_buffer_tree for ISO signals.
• update_place_bounds to include these newly created buffers. 
• Visually check these buffer cells to make sure they are ok.
• create_fp_hierarchy for these newly created buffers. 
• remove_bounds

     Step 2:  real power building for the design

• derive_pg_connection: to hooked all the existed cells. standard cell, ISO, iso_ctrl. 
• Please refer to the attached for the detailed upf commands.
• set up the voltage_area which is exactly same location as the place_bounds
• remove the standard cell placement
• place the filler_cell in the non-default voltage_area
• place the filler_cell in the default voltage_area
• pre-route standard cell to hook up the m1 power_rail for standard_cell
• remove the filler cell
• place the power switch cell
• power_straps for m2,m3,m4,m5 etc.
• hook up the power............... 

_____________________________________________________________________

FINAL and general comments:

1. upf is the trend, you need to figure out ways to use it, you can't avoid it. 
2. try to do everything inside tcl, perl is good, but you need to go out and come back and it is not convenient.

________________________________________________________________

## generate ISO_CELL_LIST

set ISO_CELL_LIST ""

foreach_in_collection rawiso [get_flat_cells *u_iso -filter "@ref_name =~ ISO*"] {

set isoName [get_attribute $rawiso full_name]

regexp  (.*)/u_iso $isoName dummy hier_iso

lappend ISO_CELL_LIST $hier_iso

}

# create power domains

##source ${LOCAL_SCRIPTS}/iso_cell_list.tcl

create_power_domain GC_TOP

create_power_domain GC_AON -elements [get_cells $ISO_CELL_LIST]

# top level connections

# Always-ON power (1.08V)

create_supply_port vcc_m1  -domain GC_TOP

create_supply_net  vcc_m1  -domain GC_TOP

create_supply_net  vcc_m1  -domain GC_AON -reuse

connect_supply_net vcc_m1  -ports vcc_m1

# vss (0.0V)

create_supply_port  vss -domain GC_TOP

create_supply_net   vss -domain GC_TOP

create_supply_net   vss -domain GC_AON -reuse

connect_supply_net  vss -ports vss

# ISGCMA domain power connection (1.08V)

create_supply_port vcc_gc -domain GC_TOP

create_supply_net  vcc_gc -domain GC_TOP

connect_supply_net vcc_gc -ports vcc_gc

# associated supply nets at the top level

set_domain_supply_net GC_TOP -primary_power_net vcc_gc -primary_ground_net vss

set_domain_supply_net GC_AON -primary_power_net vcc_m1 -primary_ground_net vss

create_power_switch gc_psw -domain GC_TOP \

  -output_supply_port {VDD vcc_gc} -input_supply_port {TVDD vcc_m1} \

  -control_port {NSLEEPIN nspleepin}  -on_state { PSWON TVDD {NSLEEPIN} } \

  -off_state { PSWOFF {!NSLEEPIN} }

map_power_switch gc_psw -domain GC_TOP -lib_cells {s2psw51udrbufx6}

create_voltage_area   -coordinate \

{663.22 4058.30   858.94 4167.48  2088.18 3831.88 2194.48 4166.50} \

-power_domain GC_AON \

-guard_band_x 3 -guard_band_y 3 \

-target_utilization 0.70000 -cycle_color