07_29_2010 Router options

 set_route_flip_chip_options

 set_route_mode_options

            zroute true or false.

 set_route_opt_strategy

 set_route_options  

 set_route_type      

           signal, clock or pg.

 set_route_zrt_common_options

 set_route_zrt_detail_options

 set_route_zrt_global_options

 set_route_zrt_track_options

07_28_2010 Expected Delivery from FE

1. netlist 
2. sdc file
3. scandef
4. clock exception list

Option

1. upf file
2. floorplan suggestion

07_28_2010 Bi-Weekly CAD meeting

The topic today is about the analog IP hookup

Concerns I collected from the meeting:

PLL

• It still could be rotated for now, it can't be rotated for 28nm
• All the analog signals are on the right, the digital signals are on the left.
• There is no build-in AVDD, AVSS pad, there are multiple avdd/avss ports/pins. It is up the PnR engineer to hook the ports to the PAD. Goal: resistance, IR drop.
• Three critical signals: REFCLKIn, CLKOUT_ANA, TP ( test point ). You can't have floating TP.
• PLL could be placed in the middle for flip-chip.
• The driving strength for the DCLK is x12, but there is no liberty file for PLL since there is no timing information for PLL and we don't need timing information for PLL. 

Serdes PHY routing channel

• Critical signals: clk and the current sources
• Routing channel cells are created to standardize the routing. To guarantee the quality. 
• 1um, 2um, 10um width routing cells, and the turning up/down routing cells.
• 1um, 2um cells don't have base layer, so they could be overlapped. 
• Different kinds of routing channel and buffer cells.
• You need a clock buffer every 500um, but you need place the 1st buffer 250um away since there are around 250um routing inside PHY.

COMPHY

• The power PADs are built-in, so no need to worry about AVDD/AVSS hookup.
• One guy complained about the misaligned pad or something, another person suggested it is because of the multiple pieces of metal for the PAD
• Chengpei complained we don't see the power mesh in the digital portion of the PHY, so this makes our IR analysis very difficult to give us last minute surprise. 

07_28_2010 ICC

07_22_2010 IR drop / power structure study

Both GC and ISP have M7 on top, but you can't expect this all the time, it is a bonus and keep changing. M7 is just for vcc_block.

Both GC and ISP are in the switching power domain, this means they have always on and switching power. vcc_m1 ( always on ) and vcc_block.  The role of vcc_m1 is to supply the power to the always on power part and the power switch cell. vcc_m1 is relative straight forward. vcc_block is tricky.

GC, power distribution structure:

           M6, M4 vertical straps.  M6 strap width is 5um, M4 strap width is 0.4um.

           There are twice M4 straps than M6 straps. half of the M4 straps are in between M6 vcc_gc and vss straps. The structure is solid. M4 straps are connected to M1, M6 is connected to M4. For the in between M6 strap M4s, the power is solid. For the "floating" M4s, they connected to the power network through M1 ( what a shame ).

           For the macro region, M5 horizontal straps are added. Macro picked up the power through M4 pins, then M5 horizontal straps, then M6 the main power straps. The power is ok or solid for macro.

  note for GC: there is a weak spot for a small area between marcos. IR drop is big, reason, there are M4 straps but it is not connected to M6 directly, the connection is like this:  M4 picked up the power from M1 and distributed to other M1 ( stdcell ),  I guess Da Xia made some last minute fix, he extended M5 straps of Macro to connect these M4s.

ISP power structure:

          Three layer power network. M6 and M2 are vertical ones. M5 is the horizontal. It is a three layer power mesh. M2 is not needed to align with M6. It is a very solid three layer power network. No special treatment is needed for macros.

    note for ISP: need to make sure there are Power Switch cell in between macros ( both horizontally and vertically , Ki-Tae only guaranteed horizontal switch cells, I think the IR will be better with switch cells vertically in between macros ). need to make sure at least a pair of M2 straps in between macros.

So Jeffrey's power mesh

1. Three layers M2, M5, M6 
2. I will use less dense M6 then ISP to give back M6 routing resource.
3. Make sure the gap between macros is wide enough for one row of switch cell
4. Make sure the gap between macros is wide enough for one column of switch cell
5. Make sure the gap between macros is wide enough for one pair of M2 straps
6. Make sure the gap between cell and boundary is wide enough for power switch cell
7. Add vcc_block, vss ring around the block.

07_20_2010 Macro hier count

1 b2d/fe

2. b2d/hi

16. b2d/mc

29. b2d/pe

2. b3d/pa

14. b3d/ra

10. b3d/se

41. b3d/sh

9. b3d/tx

07_20_2010 Power connection

stdcell: VDD/VSS ( vcc_gc/vss )

power switch cell: VDD/TVDD/VSS ( vcc_gc, vcc_m1, vss ) NSLEEPIN NSLEEPOUT

ESD: VDDON/VSS ( vcc_m1, vss )

DRO: vcc_m1/vss ( vcc_gc, vss )

07_19_2010 JCUI Macro placement flow

1. dump out the macro list with cell type and cell size

2. let icc to do the initial placement. talk with FE guy to agree on the macro placment

3. create a table for the macro placement, entries:

inst_name, cell_name, width, height, orientation ( N, FN, S, FS ), origin_x(def), origin_y (def)

4. Convert the above into def format for the placement, the macro will have the FIXED attribute.

5. load into icc, if not happy, go back to step 3.

*6 need to create a side script to convert the placement def file into my own table format.

Side note: there is NO placement grid requirement for macros, but I think I will create some kind of grid to make my life easier.

Side output: gap check. The gap is reserved to make sure enough space for switch cell placement.

GAP: the switch cell grid is 18 um vertically, the height of the macro switch cell is 3.6, so the minimum gap for macro is 18 + 3.6 = 21.6 um which is 12 row high.

07_19_2010

DEF vs TCL for macro placement

1. def, the location inside is the lower left corner

2. tcl, the origin is the location when the cell is in N orientation.

So tcl is not that straight forward, so I decide to use def instead of tcl for the macro placement,

sample code:

set_attibute [all_macro_cells] is_fixed false

read_def macro_place.def

set_attibute [all_macro_cells] is_fixed true

-Jeff

def vs fixed

I did one experiment: all the macro are fixed, I imported a def file with the cell as fixed. ICC didn't complain, it honored my def cell placement.

So the conclusion is that I will use def for the macro placement, the def file will be golden.

What is dro ???

remove_cell

report_power_domain

gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal5} -quiet]

1. Is everyone reuired to use upf ??? No, some use upf and some don't.

2. Is the vcc_m1 strap useless if there is no power switch ? ( Yes or No, it made the top level power mesh stronger, it will be hooked up at the top level. )

Several questions answered by Ki-Tae

1. Power ring around your block: to fix the floating power issue, for the narrow channel between macro and the edge. you may have power but it is not hooked to the top power network.

2. Side power switch which is used to supply the power to the macros. ( Some other people build power rings around the macro, I guess Da used several rows of power switch cells to compensate this <- Ki Tae doesn't quite like this idea since the stacks of vias may block quite some routing tracks )

3. Ki-Tae doesn't have floating piece of power which is quite clean. This should become my practice also.

4. Da had two pieces of metals shorted together, one labeled with vcc_m1, and the other vcc_gc. vcc_gc piece is not connected other vcc_gc, this is dirty which is not a problem for calibre, but it is a problem for icc_lvs.

5. Metal7 usage, this is from the top. Which may not be consistent.

So overall good practices:

1. add a ring to your block for potential stdcell power supply and avoid floating power nets.

2. reserve some space from macro to side boundary to have enough room to insert a column of power switch cells. Then you will have reasonably good power supply to the macro.

3. make sure no floating piece of power metals in your block, even if you connect them up with a thin metal.

4. use upf to set the correct voltage area, then place the power switch accordingly.

5. place the macros carefully to make sure there is room for power switch cell in between macros.

07_15_2010 Ki-Tae Power method

Da's power approach is quite messy, I guess quite some manual work.

I studied Ki-Tae's power approach, it is a little bit conservative, but I think it is pretty solid and easy to manage.

I should thank Da for his "bad"

Ki-Tae:

1. There is a vss power ring around the block, I don't know the reason yet, but it is a good approach which protect the block.

2. Defined a rectlinear voltage area, then do all the work with referring to this area. ( Da didn't define any voltage area, then I believe Da depends on some manual work ).

3. Power-switch cell placement. carefully align the macros to the power switch grid. One shot will fix all the power switch placement, remember to use the respect-hard-macro placement blockage. ( Da's approach, place power switch cell without respecting the hard macro, then put the extra powercell in between the macros, that is the reason you see three or four rows of powercell in between macros )

4. Ki-Tae made sure there is room for one row of power switch cell on the top and on the bottom.

5. Ki-Tae made room on left and right side to insert one column of power switch cell over there.

I love his power approach, easy to understand and not difficult to follow.

07_14_2010 Alex Jo IR presentation

07_14_2010 SVN

My planned data structure:

/mky/

- pnr_design_data <>

- script/pnr_script_global <>

- script/pnr_script_local <>

SVN_ROOT or home:

721 10:14 echo $HOME0

722 10:15 svnadmin create --fs-type fsfs $HOME0/scripts/svn_repo/

724 10:18 svn mkdir file://$HOME0/scripts/svn_repo/mmp2a0l

725 10:18 svn mkdir file://$HOME0/scripts/svn_repo/mmp2a0l/gc800

728 10:20 svn mkdir file://$HOME0/scripts/svn_repo/mmp2a0l/gc800/script_global

729 10:20 svn mkdir file://$HOME0/scripts/svn_repo/mmp2a0l/gc800/script_local

733 10:25 svn mkdir file://$HOME0/scripts/svn_repo/mmp2a0l/gc800/design_data

07_13_2010 ICC Place

There are two place steps for Da Xia's script:

place_opt -congestion -area_recovery -optimize_dft -num_cpus 4

psynopt -congestion -area_recovery -power

07_12_2010 ICC Setup

Logic library

Physical library

*Symbol library

Technology file

TLU+ file ( note: need to reload if the design is NOT placed yet )

Mapping file

logic0, logic1 net ???

_____________________________________________

logic library: search_path, link_library, target_library ( min_library )

physical library: set_mw_reference_library or create_mw_lib

______________________________________________

07_12_2010 gcc800_power

There are three power net: vcc_gc, vcc_m1, vss.

vcc_gc is the local power supply, vcc_m1 is the global power supply, vss is the ground.

There are two voltage area, one is always on and the other is power-switched.

For the always on area, it doesn't require power switch cell. Cut vcc_gc from the switched region and connect vcc_gc with vcc_m1.

For the switched region, add power switch cell below the power straps of vcc_gc and vcc_m1.

You need gap between macros if you have the switched power supply to macro, otherwise, your limitation is the drc rules.

07_09_2010 ICC

write_def -macro -output macro_placement.def

ICC notes:

macro_keepout_margin

write_def : the def file will include the keepout margin as halo. When you read the def back in, keepout_margin will be created according to the halo size. So personally, I prefer to have def file to take care the placement only. Leave the keepout/blockage part to icc/tcl.

hard and soft keepout: both will create placement blockage, but the difference is that: hard will create blockage for sure, soft will create blockage conditionally.

Soft macro vs hard macro vs bbox

soft macro does have child.

ICC long runtime command

report_power

07_08_2010 ICC

difference between port and terminal

port is in the logic domain, terminal is in the physical domain. One port may corresponding to multiple terminals.

get_attribute and report_attribute

get_attribute is to get specific attribute.

report_attribute is to report the full attribute of the object.

get_xxx commands could be embedded with other commands, it will return a list which be processed by other command.

report_xxx pretty much is only for display purpose only, you can't send the result to another tcl command to process.

attribute is a very powerful thing to use to label object and retrieve the label to manipulate.

get_command_option_values

gui_change_highlight -collection [get_cells -hier "*" -filter "@is_hard_macro == true"] -color red

change_selection

go x y

gui_zoom -window Layout.1 -selection

time will return the time spent on the execution of the command.

07_06_2010 Talk with Ki-Tae Kwon

Power stuff:

HOME

Set up the active window by moving cursor to it which will reduce lots of clicking.

VIM setup, use it inside your window without crapping your tool bar.

Number of windows you want to use.

• I think the reason he gave to me is convincing, tabbing has its disadvantage, you could only view one window at a time. Plus, you need to click twice to access that window.
• I think four windows should be more than enough. I remembered that Jeremy Minor always open a pair of windows when he is debugging. Maybe that is a very good practice also.

How to login to big machine by not using mlogin

• Login to a grid machine, rup without any option and you will see the list the grid machines.
• You could use rup to figure out the loading for the machine.
• You could use ssh .

Where you should launch icc ?

How to make sure your design meet some basic stuff , physical and timing view ??

07_02_2010 Talk with Ki-Tae Kwon

Technology used for mmp2a0l ( MMP2A0L ): 65 nm.

Naming convention: parent project mmp2, revision a0 ( A zero ), l: layout.

Rtl project name will be the same less L.

M2, M4, M6 are the vertical metals, M3, M5 are the horizontal metals. M6 has different electrical character from M2-M5, so you may have timing surprise when you route with M6 from Groute to Droute.

1. You have more vertical routing layers than horizontal routing layers.

2. Avoid using M6 for routing. You may build solid, stronger power network with M6.

3. Routing over macro: for gc block macros,