Concerns I collected from the meeting:
PLL
- It still could be rotated for now, it can't be rotated for 28nm
- All the analog signals are on the right, the digital signals are on the left.
- There is no build-in AVDD, AVSS pad, there are multiple avdd/avss ports/pins. It is up the PnR engineer to hook the ports to the PAD. Goal: resistance, IR drop.
- Three critical signals: REFCLKIn, CLKOUT_ANA, TP ( test point ). You can't have floating TP.
- PLL could be placed in the middle for flip-chip.
- The driving strength for the DCLK is x12, but there is no liberty file for PLL since there is no timing information for PLL and we don't need timing information for PLL.
Serdes PHY routing channel
- Critical signals: clk and the current sources
- Routing channel cells are created to standardize the routing. To guarantee the quality.
- 1um, 2um, 10um width routing cells, and the turning up/down routing cells.
- 1um, 2um cells don't have base layer, so they could be overlapped.
- Different kinds of routing channel and buffer cells.
- You need a clock buffer every 500um, but you need place the 1st buffer 250um away since there are around 250um routing inside PHY.
COMPHY
- The power PADs are built-in, so no need to worry about AVDD/AVSS hookup.
- One guy complained about the misaligned pad or something, another person suggested it is because of the multiple pieces of metal for the PAD
- Chengpei complained we don't see the power mesh in the digital portion of the PHY, so this makes our IR analysis very difficult to give us last minute surprise.
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